In recent years, research and development of nonvolatile storage devices having memory cells formed with variable resistance elements has moved forward. A variable resistance element is an element with a property that its resistance value reversibly changes based on electrical signals, and can store data corresponding to the resistance value in a nonvolatile manner.
Commonly known as a nonvolatile storage device that includes variable resistance elements is a nonvolatile storage device which includes memory cells known as 1T1R memory cells arranged in a matrix at positions at which bit lines intersect with word lines and source lines that are arranged orthogonally to the bit lines. Here, the 1T1R memory cells refer to memory cells each of which is formed by connecting in series a MOS (metal oxide semiconductor) transistor and a variable resistance element.
Patent Literature 1 discloses a nonvolatile storage device including 1T1R memory cells in which oxides having a perovskite-type crystalline structure are used as variable resistance elements.
FIG. 35 is a schematic cross-sectional view of a memory cell described in Patent Literature 1.
A memory cell 1011 is formed by electrically connecting a transistor 1006 and a variable resistance element 1010 in series.
The transistor 1006 includes, on a semiconductor substrate 1001, a source region 1002 serving as a first diffusion layer region, a drain region 1003 serving as a second diffusion layer region, and a gate electrode 1005 formed on a gate oxide film 1004.
The variable resistance element 1010 is formed by having a variable resistance layer 1008 between a lower electrode 1007 and an upper electrode 1009. Here, the variable resistance layer 1008 is a layer whose resistance value changes upon voltage application.
The drain region 1003 and the lower electrode 1007 are electrically connected.
The upper electrode 1009 is connected to a metal line serving as a bit line 1012, the gate electrode 1005 is connected to a word line, and the source region 1002 is connected to a metal line serving as a source line 1013.
Here, although Patent Literature 1 discloses Pr1-xCaxMnO3, La1-xCaxMnO3 (LCMO) and so on as the materials of the variable resistance layer 1008, there is no particular mention of electrode materials.
Furthermore, as to a method for writing into the memory cell 1011, Patent Literature 1 discloses that: application of a pulse voltage Vpp, a pulse voltage Vss, and a pulse voltage having a predetermined voltage amplitude Vwp to the upper electrode 1009, the source region 1002, and the gate electrode, respectively, changes the state from a low resistance state to a high resistance state; and inversely, application of the pulse voltage Vss, the pulse voltage Vpp, and the pulse voltage having a predetermined voltage amplitude Vwe to the upper electrode 1009, the source region 1002, and the gate electrode, respectively, changes the state from the high resistance state to the low resistance state.
Patent Literature 2 discloses a nonvolatile storage device which includes 1T1R memory cells having variable resistance elements that exhibit changes in the resistance based on a principle that is different from that of the above-mentioned variable resistance elements that exhibit changes in the resistance according to electrical signals. This storage device is called a phase-change memory.
The phase-change memory stores data by making use of the fact that a phase-change material called a chalcogenide material has different resistance between the crystalline state and the amorphous state. Data is rewritten by changing the state of the phase-change material through passage of a current therein so as to cause heat generation near its melting point. A resistance change to high resistance state (amorphization) called a reset operation is performed by control of maintaining the phase-change material at a relatively high temperature, and a resistance change to low resistance state (crystallization) called a set operation is performed by control of maintaining the phase-change material at a relatively low temperature for a sufficient period.
Moreover, Patent Literature 2 discloses that with the phase-change memory, a current necessary for data rewriting is different between the reset operation and the set operation, and the reset operation requires a relatively large current.
FIG. 36 is a cross-sectional view of the phase-change memory disclosed in Patent Literature 2.
A memory cell 1021 has a 1T1R structure in which a storage unit 1022 and an NMOS (N-channel metal oxide semiconductor) transistor 1027 are used. The NMOS transistor 1027 includes N-type diffusion layer regions 1029 and 1030 each of which can be any of a source and a drain, and a gate electrode 1031 located between the N-type diffusion layer regions 1029 and 1030.
The storage unit 1022 includes a phase change element 1024, a second metal line layer 1023 above the phase change element 1024, and a contact via 1025 and a first metal line layer 1026 below the phase change element 1024, and is connected to the N-type diffusion layer region 1029 of the NMOS transistor 1027.
The other N-type diffusion layer region 1030 of the NMOS transistor 1027 is connected to a third metal line layer 1028 via each of line layers.
Here, the second metal line layer 1023, the third metal line layer 1028, and the gate electrode 1031 of the NMOS transistor 1027 correspond to a source line, a bit line, and a word line, respectively.
Patent Literature 2 discloses adopting into a phase-change memory device a mechanism for controlling the source line and switching the current passage direction in a set operation and a reset operation.
In the reset operation requiring passage of a relatively large current, the source line is set to a predetermined high level and the bit line to a low level, and in the set operation requiring only a relatively small current, the bit line is set to a predetermined high level and the source line to a low level.
With such settings, the current direction in the reset operation is a direction in which the electric potential at the source of the NMOS transistor 1027 of the memory cell (in this case, corresponding to the electric potential at the N-type diffusion layer region 1030) is maintained at a low level almost equal to the electric potential at the semiconductor substrate. This reduces the influence of a so-called substrate bias effect in the MOS transistor, and thus the reset operation is performed with a driving capability of the transistor being high (a large current can be obtained).
On the other hand, the current direction in the set operation is a direction in which the electric potential at the source of the NMOS transistor 1027 of the memory cell (in this case, corresponding to the electric potential at the N-type diffusion layer region 1029) rises to a voltage value that is determined according to a divided voltage relationship between an on-resistance value of the NMOS transistor 1027 and a resistance value of the phase-change element 1024. This increases the influence of the substrate bias effect in the MOS transistor, and thus the set operation is performed with the current flowing in the transistor kept relatively small.
The above structure makes it easier to separately supply a current of different magnitudes suitable for each of the set operation and the reset operation, thereby allowing the outcome of each operation to be stably obtained.
Generally, to form a high density memory cell array, memory cells need to be formed in the smallest possible areas, and thus it is important to form a transistor, as well as a variable resistance element which is another structural element of each memory cell, in the smallest possible areas.
An effective way of forming a transistor in the smallest possible area is to make a gate length L of the transistor as short as possible and a gate width W of the transistor as small as possible in an efficient manner.
The following considers application of the above structure to the nonvolatile storage device disclosed in Patent Literature 1.
According to Patent Literature 1, the nonvolatile storage device shown in FIG. 35 changes the state of the memory cell 1011 from a low resistance state to a high resistance state (resistance change to high resistance state) by applying a positive voltage to the upper electrode 1009 with reference to the lower electrode 1007, that is, by setting the bit line 1012 to Vpp and the source line 1013 to 0 V.
Here, the electric potential at the source region 1002 serving as the first diffusion layer region of the transistor 1006 (in this case, the source region 1002 functions as the source of the transistor 1006) is almost equal to the electric potential at the semiconductor substrate 1001, that is, 0 V, and the substrate bias effect in the transistor 1006 is small.
On the other hand, the nonvolatile storage device changes the state of the memory cell 1011 from the high resistance state to the low resistance state (resistance change to low resistance state) by setting the bit line 1012 to 0 V and the source line 1013 to Vpp.
Here, the electric potential at the drain region 1003 that is the second diffusion layer region (in this case, the drain region 1003 functions as the source of the transistor 1006) rises to a voltage determined according to a divided voltage relationship between the resistance value of the variable resistance element 1010 and the on-resistance of the transistor 1006, and the substrate bias effect in the transistor 1006 becomes greater than in the case of the resistance change to high resistance state.
As described above, it is rational, in terms of forming the transistor of the memory cell in an optimum size, to perform the resistance change to high resistance state, which requires a current larger than for the resistance change to low resistance state, by using a current flowing in the direction in which the substrate bias effect in the transistor is smaller, because that way the transistor does not need to have a driving capability with an unnecessary margin.
It is to be noted that the semiconductor device disclosed in Patent Literature 2 also adopts the same concept that the reset operation requiring a larger current is performed using a current flowing in a direction in which the substrate bias effect in the transistor is smaller.